SYQP910

40Gb/s QSFP LR4

传输速率:
40Gbps
波长:
1310nm
传输距离:
10km
认证:
CE FCC ROHS
DDM:
YES
电源电压:
+3.3V
工作温度:
0~+70℃(商业级),-40~+85℃(工业级)
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咨询电话
+86-27-8700 1682
  • 产品描述
  • 产品应用

General Description

 

This product is a transceiver module designed for 2m-10km optical communication applications. The design is compliant to 40GBASE-LR4 of the IEEE P802.3ba standard. The module converts 4 inputs channels (ch) of 10Gb/s electrical data to 4 CWDM optical signals, and multiplexes them into a single channel for 40Gb/s optical transmission. Reversely, on the receiver side, the module optically de- multiplexes a 40Gb/s input into 4 CWDM channels signals, and converts them to 4 channel output electrical data.

The central wavelengths of the 4 CWDM channels are 1271, 1291, 1311 and 1331 nm as members of the CWDM wavelength grid defined in ITU-T G.694.2. It contains a duplex LC connector for the optical interface and a 148-pin connector for the electrical interface. To minimize  the  optical  dispersion in the long-haul system, single-mode fiber (SMF) has to be applied in thismodule.

The product is designed with form factor, optical/electrical connection and digital diagnostic interface according to the QSFP+ Multi-Source Agreement (MSA). It has been designed to meet the harshest external operating conditions including temperature, humidity and EMI interference.

 

Functional Description

 

This product converts the 4-channel 10Gb/s electrical input data into CWDM optical signals (light), by a driven 4-wavelength Distributed Feedback Laser (DFB) array. The light is combined by the MUX parts as a 40Gb/s data, propagating out of the transmitter module from the SMF. The receiver module accepts the 40Gb/s CWDM optical signals input, and de-multiplexes it into 4 individual 10Gb/s channels with different wavelength. Each wavelength light is collected by a discrete photo diode, and then outputted as electric data after amplified first by a TIA and a post amplifier. Figure 1 shows the functional block diagram of thisproduct.

A single +3.3V power supply is required to power up this product. Both power supply pins VccTx and VccRx are internally connected and should be applied concurrently. As per MSA specifications the module offers 7 low speed hardware control pins (including the 2-wire serial interface): ModSelL,  SCL, SDA, ResetL, LPMode, ModPrsL and IntL.

Module Select (ModSelL) is an input pin. When held low by the host, this product responds to 2-wire serial communication commands. The ModSelL allows the use of this product on a single 2-wire interface bus – individual ModSelL lines must be used.

Serial Clock (SCL) and Serial Data (SDA) are required for the 2-wire serial bus communication interface and enable the host to access the QSFP+ memory map.

The ResetL pin enables a complete reset, returning the settings to their default state, when a low level on the ResetL pin is held for longer than the minimum pulse  length.  During the execution of  a reset  the host shall disregard all status bits until it indicates a completion of the reset interrupt. The product indicates  this  by posting  an  IntL  (Interrupt)  signal  with  the  Data_Not_Ready bit  negated  in the memory map. Note that on power up (including hot insertion) the module should post this completion of reset interrupt without requiring a reset.

Low Power Mode (LPMode) pin is used to set the maximum power consumption for the product in order to protect hosts that are not capable of cooling higher power modules, should such modules be accidentally inserted.

Module Present (ModPrsL) is a signal local to the host board which, in the absence of a product, is normally pulled up to the host Vcc. When the product is inserted into the connector, it completes the path to ground through a resistor on the host board and asserts the signal. ModPrsL then indicates its present by setting ModPrsL to a “Low” state.

Interrupt (IntL) is an output pin. “Low” indicates a possible operational fault or a status critical to the host system. The host identifies the source of the interrupt using the 2-wire serial interface. The IntL   pin is an open collector output and must be pulled to the Host Vcc voltage on the Host board.

推荐工作条件

光电特性

时钟特性

DDM数字诊断存储器映射

收发器提供关于当前操作条件的2线串行接口(sci,SDA)对应的内存地址的内容和诊断信息。
内部校准或外部校准的诊断信息都能实现,包括接收功率监测、发射功率监测、偏置电流监测,电源电压监测和温度监测。数字诊断内存映射为特定数据字段定义如下。

 

 

引脚定义

引脚描述

PIN

Logic

Symbol

Name/Description

Notes

1

 

GND

Ground

1

2

CML-I

Tx2n

Transmitter Inverted Data Input

 

3

CML-I

Tx2p

Transmitter Non-Inverted Data output

 

4

 

GND

Ground

1

5

CML-I

Tx4n

Transmitter Inverted Data Input

 

6

CML-I

Tx4p

Transmitter Non-Inverted Data output

 

7

 

GND

Ground

1

8

LVTLL-I

ModSelL

Module Select

 

9

LVTLL-I

ResetL

Module Reset

 

10

 

VccRx

+3.3V Power Supply Receiver

2

11

LVCMOS-I/O

SCL

2-Wire Serial Interface Clock

 

12

LVCMOS-I/O

SDA

2-Wire Serial Interface Data

 

13

 

GND

Ground

 

14

CML-O

Rx3p

Receiver Non-Inverted Data Output

 

15

CML-O

Rx3n

Receiver Inverted Data Output

 

 

16

 

GND

Ground

1

 

17

CML-O

Rx1p

Receiver Non-Inverted Data Output

 

18

CML-O

Rx1n

Receiver Inverted Data Output

 

19

 

GND

Ground

1

20

 

GND

Ground

1

21

CML-O

Rx2n

Receiver Inverted Data Output

 

22

CML-O

Rx2p

Receiver Non-Inverted Data Output

 

23

 

GND

Ground

1

24

CML-O

Rx4n

Receiver Inverted Data Output

1

25

CML-O

Rx4p

Receiver Non-Inverted Data Output

 

26

 

GND

Ground

1

27

LVTTL-O

ModPrsL

Module Present

 

28

LVTTL-O

IntL

Interrupt

 

29

 

VccTx

+3.3 V Power Supply transmitter

2

30

 

Vcc1

+3.3 V Power Supply

2

31

LVTTL-I

LPMode

Low Power Mode

 

32

 

GND

Ground

1

33

CML-I

Tx3p

Transmitter Non-Inverted Data Input

 

34

CML-I

Tx3n

Transmitter Inverted Data Output

 

35

 

GND

Ground

1

36

CML-I

Tx1p

Transmitter Non-Inverted Data Input

 

37

CML-I

Tx1n

Transmitter Inverted Data Output

 

38

 

GND

Ground

1

Notes:

    1. GND is the symbol for signal and supply (power) common for QSFP+ modules. All are common within the QSFP+ module and all module voltages are referenced to this potential unless otherwise noted. Connect these directly to the host board signal common ground plane.
    2. VccRx, Vcc1 and VccTx are the receiving and transmission power suppliers and shall be applied concurrently. Recommended host board power supply filtering is shown in Figure 3 below.  Vcc  Rx, Vcc1 and Vcc Tx may be internally connected within the QSFP+ transceiver module in any combination. The connector pins are each rated for a maximum current of 500mA.

 

推荐接口电路

Recommended Power Supply Filter

 

 
 

 

结构尺寸

 

Mechanical Dimensions

 
 

 

订购须知

Order Information

 

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